Computer Organization and Architecture mcq with answers listed below.
NOTE : ANSWERS IN BELOW PAGE
(A) Multiple instructions are overlapped in execution
(B) It takes advantage of parallelism that exist among the actions needed to execute an
instruction
(C) Both A & B (D) n o n e
2 Each of the steps in a pipeline is called -------.
(A)pipe stage (B) p i p e s e g m e n t
(C) b o t h A & B (D)none
3 The throughput of an instruction pipeline is determined by -----------.
(A) how often an instruction exits the pipeline
(B) h o w o f t e n a n i n s t r u c t i o n e n t e r s t h e p i p e l i n e
(C) how often an instruction remains in the pipeline
(D) All of the above
4 A processor cycle is ---------.
(A) the time required between moving an instruction one step up the pipeline
(B) the time required between moving an instruction one step down the pipeline
(C) the memory required between moving an instruction one step up the pipeline
(D) the memory required between moving an instruction one step down the pipeline
5 The length of a processor cycle is determined by --------.
(A) the time required for the slowest pipe stage
(B) the time required for the fastest pipe stage
(C) the memory required for the slowest pipe stage
(D) the memory required for the fastest pipe stage
6 The time per instruction on a pipelined processor = --------------.
(A) time per instruction on unpipelined machine/no. of pipe stages
(B) time per instruction on unpipelined machine * no. of pipe stages
(C) no. of pipe stages/ time per instruction on unpipelined machine
(D) no. of pipe stages * time per instruction on unpipelined machine
7 Structural pipeliling hazards arise from -----------.
(A) Resource conflicts (B) d a t a c o n f l i c t s
(C) m e m o r y c o n f l i c t s (D) processor conflicts
8 Data hazards arise when -------------.
(A) an instruction depends on results of previous instruction
(B) an instruction depends on results of next instruction
(C) an instruction does not depend on results of previous instruction
(D) an instruction does not depend on results of next instruction
9 Control hazards arise from ------------.
(A) pipeliling of branches
(B) n o n p i p e l i n i n g o f b r a n c h e s
(C) p i p e l i l i n g o f a l l i n s t r u c t i o n s
(D) n o n p i p e l i n i n g o f a l l i n s t r u c t i o n s
10 ----------- has feedback and feed-forward connections.
(A) linear pipeline (B) nonlinear pipeline (C) b o t h (D)none
11 ------ is also called as static pipeline as it performs fixed functions.?
(A) linear pipeline (B) nonlinear pipeline (C) b o t h (D)none
12 ---------- is also called as dynamic pipeline as it performs different functions.
(A) linear pipeline (B) nonlinear pipeline (C) both (D)none
13 --------- allows easy functional partitioning.
(A) linear pipeline (B) nonlinear pipeline (C) both (D)none
14 In multiprocessor system where many processes needs a copy of same memory block, the
maintenance of consistency among these copies raises a raises a problem referred to as --------.
(A) cache coherence problem (B) d a t a s h a r i n g p r o b l e m
(C) p r o c e s s m i g r a t i o n p r o b l e m (D) I/O inconsistency
15 MESI stands for ------------.
(A) Modified,Exclusive,Shared,Invalid (B) Modified,Exclusive,Symmetric,Invalid
(C) Modern,Exclusive,Shared,Invalid (D) Modified,Excluding,Shared,Invalid
16 Three different types of dependences are -----------
(A) true data, name, control (B) d a t a , n a m e , c o n t r o l
(C) b o t h A & B (D) none
17 If two instructions are ------ , they can not be completely overlapped.
(A) data dependent (B) c o n t r o l d e p e n d e n t
(C) n a m e d e p e n d e n t (D) all of the above
18
--------- is the primary method used to avoid a hazard.
(A) Scheduling the code (B) A l t e r i n g t h e c o d e
(C) R e s c h e d u l i n g t h e c o d e (D) Changing the code
19
An antidependence occurs when ------------------- .
(A) instruction j writes a register or memory location that instruction i reads.
(B) instruction i and j write the same register or memory location.
(C) b o t h A & B (D) none
20 An output dependence occurs when ----------- .
(A) instruction j writes a register or memory location that instruction i reads.
(B) instruction i and j write the same register or memory location.
(C) b o t h A & B (D) none
NOTE : ANSWERS IN BELOW OF PAGE
21 Consider two instructions i and j , with i preceding j in program order.
In -------- data hazard , j tries to read a source before I writes it, so j incorrectly gets the old
value.
(A) RAW (B) W A W (C) W A R (D) RAR
22 Consider two instructions i and j , with i preceding j in program order.
In -------- data hazard , j tries to write an operand before it is written by i.
(A) RAW (B) W A W (C) W A R (D) RAR
23 In a directory-based cache coherence protocol, in ------- state, one or more processors have the
block cached and the value in memory is up to date.
(A) shared (B) u n c a c h e d (C) m o d i f i e d (D) all of these
24 In a directory-based cache coherence protocol, in ------- state, no processor has a copy of the
cache block.
(A) shared (B) u n c a c h e d (C) m o d i f i e d (D) all of these
a. Microcomputers
b. Minicomputer
c. Micromini computers
d. Mainframe computer
Ans: a
25 In a directory-based cache coherence protocol, in ------- state, exactly one processor has a copy
of the cache block and it has written the block, so the memory copy is out of date.
(A) shared (B) u n c a c h e d (C) m o d i f i e d (D) all of these
26 -------- is the node where a request originates.
(A) Local node (B) H o m e n o d e (C) R e m o t e n o d e (D)none
27 ------- is the node where the memory location and the request originates.
(A) Local node (B) H o m e n o d e (C) R e m o t e n o d e (D)none
28 ------------ is the node that has a copy of a cache block, whether exclusive or shared.
(A) Local node (B) H o m e n o d e (C) R e m o t e n o d e (D)none
29 If some combinations of instructions can not be accommodated because of resource conflicts, the
processor is said to have a ------------- .
(A) data hazard (B) s t r u c t u r a l h a z a r d (C) c o n t r o l h a z a r d (D) none
30 ----------- is a situation that prevents the next instruction in the instruction stream from executing
during its designated clock cycle.
(A) Pipeline hazard (B) C a c h e c o h e r e n c e (C) b o t h (D) none.
32. ___ is the core of the CPU.
a. CU
b. ALU
c. Memory
d. None of the above
Ans: b
32. Control Inputs tell the circuit ___ with the data.
a. When do
b. What to do
c. What and when to do
d. None of the above
Ans: c
33. ___ control unit determines the address of the next instruction be executed and loads it into the program counter.
a. Instruction Interpretation
b. Instruction sequencing
c. Instruction regulation
d. Instruction composition
Ans: b
Q Ans
1 c2 c
3 a
4 b
5 a
6 a
7 a
8 a
9 a
10 b
11 a
12 b
13 a
14 a
15 a
16 c
17 a
18 a
19 b
20 b
21 a
22 b
23 a
24 b
25 c
26 a
27 b
28 c
29 b
30 a