Big and Little Endian
Big-endian and little-endian are terms that describe the order in which a sequence of bytes are stored in computer memory.
Storing Words in Memory
• We've defined a word to mean 32 bits. This is the same as 4 bytes. Integers, single-precision floating point numbers, and MIPS instructions are all 32 bits long. How can we store these values into memory? After all, each memory address can store a single byte, not 4 bytes.
• The answer is simple. We split the 32 bit quantity into 4 bytes. For example, suppose we have a 32 bit quantity, written as 90AB12CD16, which is hexadecimal. Since each hex digit is 4 bits, we need 8 hex digits to represent the 32 bit value.
• So, the 4 bytes are: 90, AB, 12, CD where each byte requires 2 hex digits.
• It turns out there are two ways to store this in memory.
Big Endian
In big endian, you store the most significant byte in the smallest address. Here's how it would lookAddress Value
• 1000 90
• 1001 AB
• 1002 12
• 1003 CD
Little Endian
In little endian, you store the least significant byte in the smallest address. Here's how it would look Address Value• 1000 CD
• 1001 12
• 1002 AB
• 1003 90
Notice that this is in the reverse order compared to big endian. To remember which is which, recall whether the least significant byte is stored first (thus, little endian) or the most significant byte is stored first (thus, big endian).
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the programmer or compiler writer. The ISA serves as the boundary between software and hardware. We will briefly describe the instruction sets found in many of the microprocessors used today. The ISA of a processor can be described using 5 categories:
Operand Storage in the CPU
Where are the operands kept other than in memory?
Number of explicit named operands How many operands are named in a typical instruction. Operand location Can any ALU instruction operand be located in memory? Or must all operands be kept internaly in the CPU?
Operations What operations are provided in the ISA.
Type and size of operands What is the type and size of each operand and how is it specified?
The 3 most common types of ISAs are
• Stack - The operands are implicitly on top of the stack• Accumulator - One operand is implicitly the accumulator.
• General Purpose Register (GPR) - All operands are explicitely mentioned, they are either registers or memory locations.
Lets look at the assembly code of
A = B + C;
in all 3 architectures:
Stack Accumulator GPR
• SPARC (from "scalable processor architecture") is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.
• SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors.
Lets look at the assembly code of
A = B + C;
in all 3 architectures:
Stack Accumulator GPR
• SPARC (from "scalable processor architecture") is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.
• SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors.